1. Field of the Invention
The present invention relates to communication transceiver clock and data recovery (CDR) circuits, and, in particular, to a CDR incorporating Sigma-Delta circuitry.
2. Description of the Related Art
In many data communication applications, Serializer and De-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data.
At high data rates, frequency-dependent signal loss from the communications channel (e.g., the signal path between the two end points of a serial link) as well as signal dispersion and distortion can occur. As such, the communications channel, whether wired, optical, or wireless, acts as a filter and might be modeled in the frequency domain with a transfer function. Correction for frequency dependent losses of the communications channel, and other forms of signal degradation, often requires signal equalization at a receiver of the signal. Equalization through use of one or more equalizers compensates for the signal degradation to improve communication quality. Equalization may also be employed at the transmit side to pre-condition the signal. Equalization, a form of filtering, generally requires some estimate of the transfer function of the channel to set its filter parameters. However, in many cases, the specific frequency-dependent signal degradation characteristics of a communications channel are unknown, and often vary with time. In such cases, an equalizer with adaptive setting of parameters providing sufficient adjustable range might be employed to mitigate the signal degradation of the signal transmitted through the communications channel. An automatic adaptation process is often employed to adjust the equalizer's response. Equalization might be through a front end equalizer, a feedback equalizer, or some combination of both.
A clock and data recovery (CDR) circuit detects timing of the input data stream and uses such detected timing to set correct frequency and phase of a local clock from which the sampling clock for data sampling is derived. As employed herein, “placing” a sampler (latch) in a data stream requires setting a voltage threshold and clocking phase of the sampler to detect a predetermined point in a data eye. Clocking the data sampler with a clock signal with known frequency and phase derived with respect to the detected symbol timing of data allows for clock recovery of symbols within the data stream generating the data eye.
CDR circuits form a critical part of the receiver in a SerDes device. The objective of the CDR circuit is to track the phase of a sampling clock based on some criterion, such as minimized mean-squared-error (MMSE). To track the phase of a sampling clock based on a given criterion, the CDR circuit generates (timing) error samples with respect to the data sampling clock, and adaptively sets the local clock phase used to derive the data sampling clock so as to minimize the timing error with respect to the criterion between successive sampling events. The CDR circuit desirably operates so as to achieve very low target bit-error-ratio (BER) (usually, on the order of 1e-12 or 1e-15). The CDR circuits commonly employed might be broadly classified into two categories: baud-rate CDR circuits and bang-bang CDR circuits, with each class having associated advantages and disadvantages.
Known methods and devices use direct control of a receiver's VCO (RXVCO) in a digitally controlled CDR. In these methods, one or more D/A converters convert the digital control word(s) from the CDR to an analog control signal to apply to the control voltage input of the VCO. To improve receiver jitter tolerance and overcome the impact of process variation on the VCO, the resolution of the word applied to control the VCO must generally be increased. To minimize the area, power and cost of the CDR and D/A converter(s), the resolution of the control word (i.e., the number of bits contained in the word) applied to the VCO is minimized. However, with a low resolution control word, the VCO output frequency step size produces significant quantization noise. This significant quantization noise results in degraded CDR jitter tolerance to low frequency periodic jitter, especially in those applications where the incoming serial data rate is modulated by a spread spectrum clock. Increasing the resolution of the control word to improve receiver jitter tolerance increases circuit area, increases device power, and increases circuit costs.
FIG. 1 shows an exemplary clock and data recovery (CDR) circuit 100 of prior art systems including receiver VCO (RXVCO) 110. Serial data, after potentially going through linear equalization and decision feedback equalization (DFE), is applied to data slicers 102 which sample data once per unit interval (or more frequently, for oversampling data) to provide samples to phase detector 104, as well as to data recovery circuitry (not shown in FIG. 1). Sampled data provided to phase detector 104 allows CDR 100 to determine sampling clock alignment within the data eye of the received serial data, and performing clock recovery from the incoming serial data. Phase detector 104 generates sampling clock phase adjustments (up or down), thereby providing sampling clock with adjusted frequency and phase to data slicers 102. RXVCO 110 utilizes two control loops, proportional and integral, which allows for more precise tracking of the incoming data rate as its frequency deviates from the nominal rate.
A phase update request from phase detector 104 may utilize majority vote block 106, where multiple phase update requests are converted to a single up, down, or no phase update. The resulting phase update from majority vote block 106 might also be processed by optional gear shifting block 112 and multiplier 108. This processing by optional gear shifting block 112 and multiplier 108 might have a higher multiplication coefficient in the initial phase of locking to a serial data stream, providing for wider bandwidth, in order to reduce time-to-lock of RXVCO 110. After start-up, over the course of time, the gain of gear shifting block 112 and multiplier 108 is reduced, narrowing the CDR loop bandwidth, and, thus, reducing self-jitter characteristic of a non-linear bang-bang phase detector based implementation of CDR 100. The final phase update request from the gear shifting multiplier is applied as a proportional control word to RXVCO 110. RXVCO 110 might be implemented as one or more D/A converters with their outputs fed to the control voltage input(s) of an inductor-capacitor (LC) oscillator with varactor-type control of the frequency, or as a ring-based VCO with current or voltage controlling the delay of its delay stages.
FIG. 2 illustrates frequency (FVCO) and phase (ΦVCO) output of basic RXVCO-based CDR operation in the presence of proportional and integral control as a function of time. The output frequency FVCO of RXVCO 110 is a function of integral control word DI with KVCOi gain and proportional control word DP with KVCOp gain. Proportional control has a character of pulse width modulation control. Each time proportional control is applied for a limited duration of time, the proportional control causes a temporary change in frequency FVCO of RXVCO 110. As a result, phase ΦVCO of RXVCO 110 changes by some amount up or down without permanent change to frequency FVCO of RXVCO 110. The frequency (FVCO) and phase (ΦVCO) are given by relations (1) and (2).FVCO=F0+DI*KVCOI+DP*KVCOP  (1)ΦVCO=∫FVCOdt  (2)
Returning to FIG. 1, integral control, unlike proportional control, changes for an extended duration of time until limiting integrator 116 accumulates a different integer value. The integer value of limiting integrator 116 is the integral control word applied to RXVCO 110. Processing frequency might be reduced through use of decimated output of phase detector 104 that is provided by decimator 114. Again, as described previously, the integral control is modified at startup through action of gear shifting control and multiplier 109. The integer value of limiting integrator 116 is a coarse quantization of integral control of RXVCO 110, and the fractional value is not used due to RXVCO 110 implementation limitations.
FIG. 3 illustrates effects of coarse quantization of integral control of RXVCO 110 on the tracking ability of CDR 100. As shown in FIG. 3, the adjacent available integral control levels correspond to FVCO1 and FVCO2, while the target recovered clock should have frequency FCDR. Since necessary frequency is not available from RXVCO 110 due to the coarse quantization, the control results in RXVCO 110 switching between FVCO1 and FVCO2 levels in such a way that, on average, the recovered clock frequency is FCDR. Since it takes some time for limiting integrator 116 to switch from one control state to the other due to the integral control loop timing characteristics, RXVCO 110 persists with FVCO1 and FVCO2 output frequencies for extended periods of time. RXVCO 110 persisting with FVCO1 and FVCO2 output frequencies for extended periods of time causes the sampling clock phase (line 301) to deviate from the incoming data phase (line 302) before RXVCO 110 switches to a different output frequency and starts reducing the phase error. The resulting phase difference between the sampling clock of the CDR and the actual phase evident between lines 301 and 302 is an error and reduces the ability of the CDR to track the phase of the incoming serial data in the presence of noise and any spread-spectrum modulation of its nominal data rate.